The Mixed Logic Style based Low Power and High Speed One-bit Binary adder for SOI designs AT 32NM Technology
Chaitanya Kommu1, A Daisy Rani2
1Chaitanya Kommu, Instrument Technology, Andhra University, Visakhapatnam, Andhra Pradesh, India.
2Dr. A Daisy Rani, Instrument Technology, Andhra University, Visakhapatnam, Andhra Pradesh, India.

Manuscript received on November 15, 2019. | Revised Manuscript received on November 23, 2019. | Manuscript published on November 30, 2019. | PP: 361-366 | Volume-8 Issue-4, November 2019. | Retrieval Number: D6903118419/2019©BEIESP | DOI: 10.35940/ijrte.D6903.118419

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Abstract: Binary adders are the fundamental building blocks to construct Data Processing arithmetic units. A novel one-bit full adder is presented in this paper which is designed by Mixed logic design style. In addition to small size transistors and reduced transistor activity compared to conventional CMOS (Complementary Metal Oxide Semiconductor) gates, it provides the priority between the High logic and Low logic for the computation of the output. Various logic topologies are used to design the one-bit full adder like High-Skew(Hi-Skew), Low-Skew(Li-Skew), TGL (Transmission Gate Logic) and DVL (Dual Voltage Logic). This new approach gives the better operating speed, low power consumption compared to conventional logic design by reducing the transistors activity and by improving the driving capability. This Mixed logic style provides 83.53% average power consumption and Propagation Delay of 14.02% at 0.8v. The H-SPICE simulation tool is used for construction and evaluation of the Full adder logic at different voltages. The 32nm model file is used for MOS transistors.
Keywords: CMOS Logic, Low Power CMOS, Pass Transistors, Skew Gates Transmission Gate.
Scope of the Article: Fuzzy Logics.