An Efficient VLSI Design of AES Cryptography in Memory Implementation
Bijjam.Swathi1, Manchalla. O.V. P.Kumar2, G.Marlin Sheeba3, M.Kiran4, Y.Sudarsana Reddy5
1Bijjam.Swathi, Mtech student, department of ECE, Gokaraju Rangaraju Institute of Engineering and Technology. Hyderabad, TS, India.
2Manchalla.O.V.P.Kumar, PH.D scholar, Department of ECE, Sathyabama Institute of science and technology, Chennai, TN, India.
3Dr. G.Marlin Sheeba, Assoc. Professor, Department of Electronics and Telecommunication Engineerinng,. Sathyabama Institute of science and technology, Chennai, TN, India.
4M.Kiran, Assoc. Professor, Department of ECE, Gokaraju Rangaraju Institute of Engineering and Technology. Hyderabad, TS, India.
5Y.Sudarsana Reddy, Assoc. Professor, Department of ECE, Gokaraju Rangaraju Institute of Engineering and Technology. Hyderabad, TS, India.
Manuscript received on November 15, 2019. | Revised Manuscript received on November 23, 2019. | Manuscript published on November 30, 2019. | PP: 1796-1801 | Volume-8 Issue-4, November 2019. | Retrieval Number: C6188098319/2019©BEIESP | DOI: 10.35940/ijrte.C6188.118419
Open Access | Ethics and Policies | Cite | Mendeley | Indexing and Abstracting
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper depicts a novel sub bytes strategy for executing the executing the advanced encryption standard (AES) algorithm that offers a considerably enhanced cryptographic strength. Our strategy depends on composite field math randomization, which involves a low cost of execution while not adjusting the algorithm, does not decrease the recurrence of the work and maintains an ideal similarity to the distributed standard. In this document, we suggest a fast and knowledgeable execution of AES in memory (AIM) to scramble the whole part of the memory only when needed. We use NVM’s intrinsic logic working ability to implement the AES algorithm instead of adding extra processing parts to the cost-sensitive memory. The proposed design is implemented using Modelsim 6.4 C and Xilinx tool Verilog HDL and simulated. The proposed framework actualized in FPGA Vertex or Spartan-3.The proposed AES system has been made into an IP and effectively connected in encryption application.
Keywords: AES Algorithm, Verilog HDL, FPGA, MEMORY UNIT.
Scope of the Article: Algorithm Engineering.