Optimization of CMOS 8-bit Counter using SLA and Clock Gating Technique
Upwinder Kaur1, Rajesh Mehra2

1Upwinder kaur, Department of Electronics and Communication Engineering, National Institute of Technical Teachers„ Training & Research, Chandigarh, India.
2Rajesh Mehra, Associate Professor, Department of Electronics and Communication Engineering, National Institute of Technical Teachers„ Training & Research, Chandigarh, India.

Manuscript received on 21 July 2013 | Revised Manuscript received on 28 July 2013 | Manuscript published on 30 July 2013 | PP: 44-50 | Volume-2 Issue-3, July 2013 | Retrieval Number: C0704072313/2013©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: The development of digital integrated circuits is challenged by higher power consumption. Scaling helps to improves transistor density, increase speed and frequency of operation and hence higher performance. As voltages scale downward with the geometries threshold voltages must also decrease to gain the performance advantages of the new technology but leakage current increases exponentially. Power consumption has a static component coming from the leakage of inactive devices and a dynamic component coming from the switching of active devices. It has been proved that clock signal consumes a high dynamic power as the clock net has one of the highest switching densities. The clock signal keeps changing its state in certain time points according to its frequency even if the logic output doesn’t change “hold mode”. Switching power dissipation may eventually dominate total power consumption in sub micron technology. Glitches or unwanted transitions consume about 20%-70% of Dynamic Power and needs to be eliminated. Therefore, the main aim of this thesis work is to reduce power consumption due to both glitches and Clock switching. In this thesis work, the novel approaches are proposed for reducing dynamic power with minimum possible power consumption and delay trade off. A novel approach for reducing dynamic power i.e. SLA (State Look Ahead) and Clock Gating has been proposed. Proposed parallel counter shows 66.04% power improvement as compared to Kakarountas counter and 54.3% power reduction as compared to Alioto’s counter. Abdel’s counter with proposed parallel counter shows 29.9% power reduction. Maximum operating frequency is also improved in proposed parallel counter. By using pass transistors drawback of large area in Abdel’s counter is optimized in proposed circuit. So the proposed parallel 8-bit counter is optimized in terms of speed, power and area as compared to previous counter designs. Use of Pass Transistor is helpful in reducing or eliminating the glitches from circuit. Clock Switching power reduction designs are also proposed which are more power efficient and have less delay as compared to existing techniques.
Keywords: Dynamic Power, Integrated Clock Gating, Pass Transistor, State look Ahead Logic, Switching Activity.

Scope of the Article: Discrete Optimization