Low Voltage Full Swing Fin FET Hybrid Full Adder
Nancharaiah Vejendla1, R. Ramana Reddy2, N. Balaji3 

1Nancharaiah Vejendla, Research scholar, Dept. of ECE, JNTU Kakinada, A.P, India.
2Dr.R. Ramana Reddy, Professor & Head of ECE, JNTUACEP, Pulivendula, A.P, India.
3Dr.N. Balaji, 3Professor, Department of ECE, UCOE, Narasaraopet, JNTUK, A.P, India.

Manuscript received on 01 March 2019 | Revised Manuscript received on 06 March 2019 | Manuscript published on 30 July 2019 | PP: 4253-4262 | Volume-8 Issue-2, July 2019 | Retrieval Number: B2468078219/19©BEIESP | DOI: 10.35940/ijrte.B2468.078219
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: In this research paper, CMOS and Fin FET based hybrid Full Adders operating at low voltages with low power dissipation are proposed. The proposed CMOS based circuit is compared with few existing hybrid full adders in terms of average power dissipation and power-delay-product (PDP). The designed CMOS based hybrid adder achieves lower power dissipation and low PDP compared to other hybrid adders over a voltage range of 0.6V to 1V. The proposed CMOS implementation of hybrid full adder fails at 0.5V to produce full swing output. To solve this full swing problem, the proposed hybrid full adder is implemented using Fin FETs which produce full output voltage, lower power and low PDP comparing with CMOS implementation. The circuits are designed with HSPICE tool in 32nm predictive technology model (PTM).
Keywords: Delay, Fin FET, Hybrid Full Adder (HFA), Conventional MOS (CMOS), Power-Delay-Product, Power Dissipation.

Scope of the Article: Software Product Lines