Low Power High Speed Ternary Content Addressable Memory
Venkataramana Datti1, P.V.Sridevi2
1Venkata Ramana Datti, Department of Electronics and Communication Engineering, GMR Institute of Technology, Rajam, (A.P.), India.
2P. V. Sridevi, Professor, Department of Electronics and Communication Engineering, Andhra University, Visakhapatnam, India.
Manuscript received on 03 March 2019 | Revised Manuscript received on 09 March 2019 | Manuscript published on 30 July 2019 | PP: 2454-2458 | Volume-8 Issue-2, July 2019 | Retrieval Number: B2020078219/19©BEIESP | DOI: 10.35940/ijrte.B2020.078219
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Compared to Binary Content Addressable Memory (BiCAM) there are many applications for Ternary Content Addressable Memory (TCAM) as a search engine. But TCAM consumes more power than BiCAM. So, the saving of TCAM power consumption is the main objective of numerous designs. Precharge phase of the TCAM leads to more power consumption. Newly, a precharge free NOR type BiCAM has been suggested but it takes more time for its operation. Here, precharge free high speed NOR type TCAM is proposed. The proposed TCAM architecture takes power same as precharge free NOR type TCAM but its delay has been reduced by 84% . Simulations performed with cadence 45-nm technology at the supply voltage of 1V.
Index Terms: Matchline Structure, NOR type TCAM , Precharge, Ternary CAM.
Scope of the Article: Low-power design