4-Bit Multiplier Design using CMOS Gates in Electric VLSI
N. Soumya1, Kayam Sai Kumar2, K. Raghava Rao3, S. Rooban4, P. Sampath Kumar5, Gurram Narendra Santhosh Kumar6
1N. Soumya, Assistant Professor, Mallareddy Institute of Technology, Secundrebad, India.
2Kayam Sai Kumar, Research Scholar, Guntur, KLEF, (A.P) India.
3K. Raghava Rao, Professor, Guntur, KLEF, India.
4S. Rooban, Associate Professor, KLEF University, (A.P) India.
5P. Sampath Kumar, Professor, Mallareddy Institute of Technology, India.
6Gurram Narendra Santhosh Kumar, Research Scholar, KLEF, (A.P) India.
Manuscript received on 03 March 2019 | Revised Manuscript received on 08 March 2019 | Manuscript published on 30 July 2019 | PP: 1172-1177 | Volume-8 Issue-2, July 2019 | Retrieval Number: B1742078219/19©BEIESP | DOI: 10.35940/ijrte.B1742.078219
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In the electronics sector, in particular digital signal processing (DSP), picture processing or even math systems in microprocessors, a quick as well as effort modifier is often required. Multiplier really is an significant component that significantly adds to the system’s complete energy usage. In VLSI, multipliers of different bit-widths are often needed from computers to particular embedded systems for implementation. To be that much further energy than supplementary TTL, logic type similarities relying on complete CMOS devices have currently been revealed. The most significant but also commonly adopted metrics of evaluating delay, energy dispersion and region of multiplier layout performance.
Index Terms: 4 Bit Multiplayer, Electrical VLSI, Low Power, High Speed.
Scope of the Article: Discrete Optimization