Power Quality Event Detection and Classifier Architecture on FPGA for Smart Meters
Prathibha.E1, Hinsermu Alemayehu2, A.Manjunatha3
1Dr.Prathibha.E*, Department of Electrical and Computer Engineering, Adama Science and Technology university, Adama, Ethiopia.
2Hinsermu Alemayehu, Department of Electrical and Computer Engineering, Adama Science and Technology university, Adama, Ethiopia.
3Dr.A.Manjunatha, principal at Sri Krishna institute of technology, Bangalore, Karnataka. India.
Manuscript received on May 11, 2020. | Revised Manuscript received on May 17, 2020. | Manuscript published on May 30, 2020. | PP: 2617-2521 | Volume-9 Issue-1, May 2020. | Retrieval Number: A3027059120/2020©BEIESP | DOI: 10.35940/ijrte.A3027.059120
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Smart meters have been developed to capture PQ events, detect the event, compress events and characterize events. The events are stored in local memory of smart meter as well are transmitted over communication channel. The smart meter hardware that performs complex signals processing activity such as event detection, classification and compression need to be implemented on reconfigurable platforms. FPGAs are used in smart meters as they support reconfigurability and also has inbuilt memory modules, processor modules and additional features for interfacing. High speed low power area efficient architectures for computation of Dual Tree Complex Wavelet Transform (DTCWT).
Keywords: Dual Tree Complex Wavelet Transform, power quality disturbances, Smart meter.
Scope of the Article: Wavelet Transform