Implementation of Quaternary Divider for Performance Optimization
Shweta Hajare1, Monica Kalbande2, Tejswini Panse3, Pravin Dakhole4
1Shweta Hajare*, Department of Electronics Engineering, Yeshwantrao Chavan college of Engg, Nagpur, India.
2Monica Kalbande, Department of Electronics Engineering,Yeshwantrao Chavan college of Engg, Nagpur, India.
3Tejswini Panse, Department of Electronics Engineering,Yeshwantrao Chavan college of Engg, Nagpur, India.
4Pravin Dakhole, Department of Electronics Engineering, Yeshwantrao Chavan college of Engg, Nagpur, India.
Manuscript received on April 02, 2020. | Revised Manuscript received on April 21, 2020. | Manuscript published on May 30, 2020. | PP: 992-995 | Volume-9 Issue-1, May 2020. | Retrieval Number: A2199059120/2020©BEIESP | DOI: 10.35940/ijrte.A2199.059120
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In VLSI technology, designers concentrations is on area required and on performance of the device. In this design power consumption is one of the major concerns due to increase in chip density, continuous and decline in size of CMOS circuits and frequency at which circuits are operating. High-speed divider is an significant issue of high-speed computing. This paper presents quaternary division algorithm .This algorithm involves detect zero circuit designed with transmission gate. This proposed algorithm is faster than binary division algorithm as well as radix 4 SRT division algorithm in terms of speed & power. This type of fast divider can be used for the design of Arithmetic Logic unit.
Keywords: Quaternary transmission gate (T-gate), Quaternary Delta literal circuit, Quaternary detect zero circuit.
Scope of the Article: Cross Layer Design and Optimization