Low Power 4-2 Compressor for Arithmetic Circuits
Riya Garg1, Suman Nehra2, B. P. Singh3

1Ms. Riya Garg, Department of Electronics and communication, FET-MITS (Deemed University), Lakshmangarh (Rajasthan), India.
2Mrs. Suman Nehra, Drpartment of Electronics and communication, MITS (Deemed University), Lakshmangarh (Rajasthan), India.
3Prof. B. P. Singh, Department of Electronics and communication, FET-MITS (Deemed University), Lakshmangarh (Rajasthan), India.

Manuscript received on 21 March 2013 | Revised Manuscript received on 28 March 2013 | Manuscript published on 30 March 2013 | PP: 204-207 | Volume-2 Issue-1, March 2013 | Retrieval Number: A0507032113/2013©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: Most of the VLSI circuits used adders as a crucial portion, since they form the base element of all arithmetic functions. Increasing demand for portable equipments requires area and power efficient VLSI circuits. This paper presents 4-2 compressor using two different 8T full adder designs. The aim of this paper is to reduce the power consumption of 4-2 compressor without compromising the speed and performance. All pre-layout and post-layout simulations have been performed at 45nm technology on Tanner EDA tool version 12.6 and compared in terms of power consumption, power-delay product (PDP) over various input voltages, temperatures and frequencies
Keywords: 2T (2 transistors), 3T, 8T and PDP

Scope of the Article: Nanometer-Scale Integrated Circuits