CSD Based VLSI Architecture for NN Based Image Compression
Lakshmi Kiran Mukkara1, K. Venkata Ramanaiah2
1Lakshmi Kiran Mukkara, Research Scholar, Department of Electronics & Communication Engineering, YSR Engineering College of Yogi Vemana University, Proddatur (Andhra Pradesh), India.
2K. Venkata Ramanaiah, Associate Professor, Department of Electronics & Communication Engineering, YSR Engineering College of Yogi Vemana University, Proddatur (Andhra Pradesh), India.
Manuscript received on 26 February 2019 | Revised Manuscript received on 13 March 2019 | Manuscript Published on 17 March 2019 | PP: 50-53 | Volume-7 Issue-ICETESM18, March 2019 | Retrieval Number: ICETESM13|19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Images take huge amount of transmission bandwidth and memory storage space. Image compression can handle these issues properly. Especially, neural network (NN) structures can be used since few decades for this purpose because of its reliability, programmability, parallel computing capability, robustness and so on which are not possible with conventional techniques. VLSI implementation of NN structures is limited due to its complexity and power consumption. In this paper a novel approach is proposed for low loss image compression VLSI architecture for efficient power and speed by using pipelined CSD algorithm. The proposed low loss image compression can be implemented on FPGA by using Xilinx Vivado.
Keywords: Canonic Signed Digit, Neural Network, FPGA Structures, VLSI Design.
Scope of the Article: VLSI Algorithms