Efficient Design to Error Detection in EG-LDPC Codes
Anvesh Thatikonda1, C Chitra2
1Anvesh Thatikonda, Research Scholar, Dept. of E.C.E, Sri SatyaSai University of Technology & Medical Sciences, Sehore, Bhopal-Indore Road, Madhya Pradesh, India.
2Dr.C Chitra, Research Guide, Dept. of E.C.E, Sri Satya Sai University of Technology & Medical Sciences, Sehore, Bhopal Indore Road, Madhya Pradesh, India.

Manuscript received on January 05, 2020. | Revised Manuscript received on January 25, 2020. | Manuscript published on January 30, 2020. | PP: 4905-4907 | Volume-8 Issue-5, January 2020. | Retrieval Number: E5079018520/2020©BEIESP | DOI: 10.35940/ijrte.E5079.018520

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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: Capability to correct large number of errors Majority logic decodable codes is suitable for memory applications. The memory access time as well as area of utilization and the decoding time is reducing using Majority Logic Decoder. In Euclidean Geometry Low-Density Parity-Check (EG-LDPC) codes there exits fault secure detector which are used for error correction. Because EG-LDPC codes are widely used it will avoid high complexity in decoding. Majority logic decidable which is a one step is a technique similar to a class of Euclidean geometry low density parity check (EG-LDPC) codes. This method is very effective for EG-LDPC codes as shown in the result. The number of errors are detected by the majority logic decode further it can be used for correct the errors which occurred.
Keywords: EG-LDPC, Decoding, Encoding.
Scope of the Article: Low-power Design.