FPGA Implementation of Encryption and Decryption of a Message using Optimized Reconfigurable Reversible Gate
K. Rajesh1, G. Umamaheswara Reddy2 

1K. Rajesh, Department of Electronics & Communication Engineering, Sri Venkateswara University, Tirupati, India.
2Prof. G. Umamaheswara Reddy, Department of Electronics & Communication Engineering, Sri Venkateswara University, Tirupati, India.

Manuscript received on 21 March 2019 | Revised Manuscript received on 27 March 2019 | Manuscript published on 30 July 2019 | PP: 1654-1658 | Volume-8 Issue-2, July 2019 | Retrieval Number: B2396078219/19©BEIESP | DOI: 10.35940/ijrte.B2396.078219
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: The prime incentive to learn reversible computation is that it is the best efficient way to reduce heat dissipation than any other conventional methods. The major condition for reversibility is that there is a one-to-one connection between each input and output vectors and it has received a huge significance because of there no information loss throughout the reversible computation which results in reduces the power dissipation. Here, we proposed the design of encryption/decryption of the data schemes by using reversible computing. In this regard, a basic building block is designed for encryption design is simply cascading of a 4-bit reversible gates and it is performed every 4-variable reversible functions, for this intention a new reconfigurable reversible gate (RRG) is proposed and is designed with the use of basic reversible gates like NOT gate, CNOT gate, Toffoli gate, and Fredkin gates. In this work, the encryption/decryption of an 8-bit data is proposed and the Simulation results of encryption/decryption of the circuits using reversible gates are also presented. The gate count, delay, constant inputs, and the garbage outputs are calculated. The complete Simulation and the synthesis process can be finished with the Xilinx ISE 14.7 version and it is dumped on the FPGA Zynq board.
Index Terms: Decryption, Encryption, FPGA- Field Programmable Gate Array, Reversible Computation, RRG – Reconfigurable Reversible Gate.

Scope of the Article: Encryption Methods and Tools