Improving Correctness of Logic Circuit Using Self-Healing Built-In Logic Test Module in FPGA using Dynamic Partial Reconfiguration
Manjith B.C. 

Dr. Manjith B.C., Department of Computer Science and Engineering, National Institute of Technology Puducherry, Karaikal
Manuscript received on 15 March 2019 | Revised Manuscript received on 21 March 2019 | Manuscript published on 30 July 2019 | PP: 2024-2034 | Volume-8 Issue-2, July 2019 | Retrieval Number: B2104078219/19©BEIESP | DOI: 10.35940/ijrte.B2104.078219
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Abstract: As cloud servers continue to receive more and more applications and data, it starts using ASIC and FPGAs as accelerators for processor intensive applications. Because of the reconfiguration nature of FPGAs, it become a good choice rather than ASIC on cloud. Encryption is an application which happens frequently on cloud and takes lot of processor cycles which can be shifted to hardware accelerator for execution. The security of hardware circuit which is transferred as bitstream to the FPGA board is of major concern for security critical applications. The article proposes a novel logic authentication module that can check the authentication or correctness of selected parts of logic circuit any time after the circuit is burned into FPGA. In the proposed work, Advanced Encryption Standard (AES) circuit parts are checked for correctness by using in-built Secure Hash Algorithm (SHA) and corrected by Dynamic Partial Reconfiguration (DPR). After the bitstream is burned into FPGA, a proposed software module can select a part or entire circuit for checking authentication with multiple sample inputs. Without the proposed method, any error after the circuit creation cannot be identified or corrected. Additionally, small faults in the circuit is corrected by DPR without loading the entire module. Totally 16 Benchmarks were created to check the correctness of the proposed system. Usage of DPR for circuit correction saves about 97% of time compared to reconfiguring the entire module.
Index Terms: AES, Circuit Correctness, Dynamic Partial Reconfiguration, SHA, Hash Code.

Scope of the Article: Nanometer-Scale Integrated Circuits