Efficient Comparator Design for Motion Estimation on FPGA
Jaya Koshta1, Kavita Khare2 

1Jaya Koshta, Department of Electronics & Communication Engg., MANIT, Bhopal, India.
2Kavita Khare, Department of Electronics & Communication Engg., MANIT, Bhopal, India.

Manuscript received on 14 March 2019 | Revised Manuscript received on 19 March 2019 | Manuscript published on 30 July 2019 | PP: 1118-1123 | Volume-8 Issue-2, July 2019 | Retrieval Number: B1656078219/19©BEIESP | DOI: 10.35940/ijrte.B1656.078219
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: Motion Estimation(ME) operationinvolves predicting the frames and identifying motion vectors sothat redundancy can be exploited by eliminating the transfer ofsimilar information between successive frames.The most efficientand simple technique to estimate the motion vectors is Summation ofAbsolute Difference(SAD) where comparator forms one of an elemental component in SAD computation.This paper proposes two different comparator designs where propoundcircuit I is based on efficient look ahead comparator andpropound circuit II uses alteredone’s complement and conditional sum adder method. Results shows that propound circuit I reduces delay by 23%but with 16% increase in number of slice LUTs whereas the propoundcircuit II reduces delay by 11% and gives 33% reduction in number of slice LUTsas compared to traditional circuit. The propound hardwarecircuits are implemented on Virtex 7 FPGA and synthesized using Verilog as HDL language on Xilinx ISE 14.2.
Index Terms: HEVC, Motion Estimation, Summation of Absolute Difference, Look-Ahead Comparator, Conditional Sum Adder.

Scope of the Article: Energy Efficient Building Technology