Strained SI/SIGE/SI Nano-Channel Hoi Mosfet
Lalthanpuii Khiangte1, Rudra Sankar Dhar2

1Lalthanpuii Khiangte, Department of Electronics and Communication Engineering, National Institute of Technology, Aizawl (Mizoram), India.
2Rudra Sankar Dhar, Department of Electronics and Communication Engineering, National Institute of Technology, Aizawl (Mizoram), India.
Manuscript received on 23 July 2019 | Revised Manuscript received on 03 August 2019 | Manuscript Published on 10 August 2019 | PP: 1227-1230 | Volume-8 Issue-2S3 July 2019 | Retrieval Number: B12290782S319/2019©BEIESP | DOI: 10.35940/ijrte.B1229.0782S319
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Abstract: Strained Si technology has headed in the development of single or dual channel strained silicon MOSFETs devices. Comprehending the need of advancement in recent technologies with miniaturized features, developing a novel MOSFET on ultrathin double strained Si with strained SiGe sandwiched in between and forming a tri-channel MOSFET has been the crux of this present research. Incorporation of quantum carrier confinement effect on the ultrathin dual strained Si layers in the channel has been implemented to counterbalance the threshold voltage roll-off induced by the strained layers. A comparison of the conventional strained silicon on relaxed silicon-germanium with double strained silicon channel MOSFET has been perceived leading to eloquent drain current enhancement of ~49% with a small reduction in the threshold voltage caused by the additional bottom strained Si layer. Further, 100nm and 50nm channel length have been compared and a superior device characteristic for the reduced device dimension is attained as the prominence of velocity overshoot is more in short channel device approaching to quasi-ballistic transport in the channel region.
Keywords: Double Strained Si; SOI; Strained Sige Velocity Overshoot; Threshold Voltage; MOSFET; HOI; Transconductance (Gmmax); Quantum Confinement; DIBL.
Scope of the Article: Nano electronics and Quantum Computing