Proposed Low-Power FPGA Architecture using an Autonomous Fine-Grain Power Gating
Kiruthiga M1, Prakasam P2, L.M.I Leo Joseph3

1Kiruthiga M, PG Scholar VLSI Design, Department of Electronics and Communication Engineering, MIET Engineering College, Trichy, (Tamil Nadu), India.
2Dr. Prakasam P, Professor, Department of Electronics and Communication Engineering, Tagore Institute of Engineering and Technology, Salem (Tamil Nadu), India.
4Prof. L.M.I Leo Joseph, Associate Professor, Department of Electronics and Communication Engineering, MIET Engineering College, Trichy  (Tamil Nadu), India.

Manuscript received on 18 June 2012 | Revised Manuscript received on 25 June 2012 | Manuscript published on 30 June 2012 | PP: 60-65 | Volume-1 Issue-2, June 2012 | Retrieval Number: B0203051212/2012©BEIESP
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Abstract: FIELD-PROGRAMMABLE gate arrays (FPGAs) are widely used to implement special-purpose processors. FPGAs are economically cheaper for low quantity production because its function can be directly reprogrammed by end users. FPGAs consume high dynamic and standby power compared to custom silicon devices. This paper presents a low power field-programmable gate array (FPGA) based on lookup table (LUT) level fine-grain power gating with small overheads. The activity of each LUT can be easily detected using the proposed power gating technique by exploiting features of asynchronous architectures. In this paper, the novel Logic Block utilizing the LUT with autonomous power gating has been proposed and the developed model has been simulated and synthesized in a selected target device. Also the power analysis has been carried out and it has been found that using the proposed fine-grain power gating method, the FPGA consumes only 34 uW.
Keywords: FPGA, Power Gating, Logic Block, Lookup Table

Scope of the Article: Low-power Design