Volume-1 Issue-6, January 2013 – International Journal of Recent Technology and Engineering (IJRTE)

F0427021613

IJRTE Journal — Mon, 14 Nov 2022 07:11:06 +0000

Artificial Neural Network, Decision Tree and Statistical Techniques Applied for Designing and Developing E-mail Classifier
H.S. Hota¹, Akhilesh Kumar Shrivas², S.K. Singhai³
¹Dr. H.S. Hota, Asst. Professor, Department of Computer and IT, Guru Ghasidas University Bilaspur, (C.G.), India.
²Akhilesh Kumar Shrivas, Research Scholar, CV. Raman University, Bilaspur (C.G.), India.
³Dr. S.K. Singhai, Department of Electronics Engineering, Govt. Engineering College, Bilaspur (C.G.), India.
Manuscript received on 21 January 2013 | Revised Manuscript received on 28 January 2013 | Manuscript published on 30 January 2013 | PP: 164-169 | Volume-1 Issue-6, January 2013 | Retrieval Number: F0427021613/2013©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: Due to increased bandwidth and strong infrastructure available for accessing internet, internet users are growing rapidly. Internet users frequently use e-mail for fast data communication of audio, vedio and textual data but at the same time they are facing problem due to unwanted e-mail known as spam e-mail. In order to filter this unwanted e-mail, a classifier must be placed in the network or in computer. In this paper three different types of technique: Artificial Neural Network (ANN), Decision tree and statistical technique are explored for designing and developing e-mail classifier. Experimental work has been performed on e-mail data set obtained from UCI repository site and is partitioned into three different partitions to find out best suitable partition to be applied for various model. A suitable ensemble model is chosen based on various error measures calculated after training and testing the models. A final ensemble model is measured in terms of accuracy, precision, recall, Fmeasure and Gain Chart. Highest accuracy of 94.35% is obtained in case of ensemble of C5.0 and SVM with 60%-40% (training – testing) partition.
Keywords: C5.0, Support Vector Machine (SVM), Artificial Neural Network (ANN), Ensemble model.
Scope of the Article: Computer Network

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F0447021613

IJRTE Journal — Mon, 14 Nov 2022 07:04:30 +0000

Comparative Study between Wireless Regional Area Network (IEEE Standard 802.22) and WiMAX and Coverage Planning of a Wireless Regional Area Network Using Cognitive Radio Technology
Santa Rahman¹, Nahid Hossain², Nizam Sayeed³, M.L. Palash⁴
¹Santa Rahman, Department of Applied Physics, Electronics & Communication Engineering, University of Dhaka, Dhaka, Bangladesh.
²Md. Nahid Hossain, Department of Applied Physics, Electronics & Communication Engineering, University of Dhaka, Dhaka, Bangladesh.
³Md. Nizam Sayeed, Department of Applied Physics, Electronics & Communication Engineering, University of Dhaka, Dhaka, Bangladesh.
⁴M. L. Palash, Lecturer, Department of Applied Physics, Electronics & Communication Engineering, University of Dhaka, Dhaka, Bangladesh.
Manuscript received on 21 January 2013 | Revised Manuscript received on 28 January 2013 | Manuscript published on 30 January 2013 | PP: 161-163 | Volume-1 Issue-6, January 2013 | Retrieval Number: F0447021613/2013©BEIESP
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Abstract: The first worldwide application of cognitive radio (CR) networks in unlicensed television broadcast bands is IEEE 802.22 wireless regional area network (WRAN). This paper introduces the implementation of IEEE 802.22 Wireless Regional Area Network (WRAN) for broadband Internet access in sub-urban areas. We have investigated how CR through dynamic spectrum access facilitates the efficient use of underutilized spectrum (white spaces). To do this, we have analyzed a coverage planning for WRAN and compared it with a traditional wireless communication standard, IEEE standard 802.16e. We have also observed the comparison for different modulation schemes and shown the results in graphical form.
Keywords: CR, TVWS, WiMAX, WRAN.
Scope of the Article: Wireless Communication

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F0423021613

IJRTE Journal — Mon, 14 Nov 2022 07:00:15 +0000

Arithmetic and Logic Unit Designing Using Reversible Logic Gate
Divyansh Mathur¹, Arti Saxena², Abneesh Saxena³
¹Divyansh Mathur, Student IVth Year, Department of Electronics and Communication, PSIT-COE, Kanpur (U.P.), India.
²Arti Saxena, Head of Department, Department of Electronics and Communication, PSIT-COE, Kanpur (U.P.), India.
³Abneesh Saxena, Department of JWM, Ordnance Factory, Kanpur (U.P.), India.
Manuscript received on 21 January 2013 | Revised Manuscript received on 28 January 2013 | Manuscript published on 30 January 2013 | PP: 157-160 | Volume-1 Issue-6, January 2013 | Retrieval Number: F0423021613/2013©BEIESP
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Abstract: Owing to its unique technique of One-to-One Mapping between the inputs and the corresponding outputs, the ReversibleLogicGates are now finding profound as well as promising applications in emerging growing paradigms such as Quantum Computing, Quantum Dot Cellular Automata, Optical Computing, Digital Signal Processing, Low Power CMOS Design, Nanotechnology etc. The Reversible Logic has received great attention in the past recent years due to its ability in reducing the power dissipation, the major concern in digital designing. To generate a useful gate function the Reversible Gates require constant inputs, called Ancillary Inputs, and some additional unused outputs, called Garbage Outputs, in order to maintain the reversibility of the digital circuits. The paper presents a novel design of different Arithmetic and Logic Units such as Half Adder, Half Subtracter and 1-Bit Comparator, using the existing Reversible Gates and the proposed new Reversible CNOT, BJN, and Peres Gates.
Keywords: CNOT Gate, Peres Gate, BJN Gate.
Scope of the Article: Fuzzy Logics

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F0438021613

IJRTE Journal — Mon, 14 Nov 2022 06:54:26 +0000

Analyzing Data Collection Strategies Using Mobile Sink
Aparna A. Kamble¹, Vivek S. Deshpande²
¹Aparna Kamble, Department of Information Technology, MITCOE College of Engineering, Pune University, Pune (Maharashtra), India.
²V. S. Deshpande, Department of Information Technology, MITCOE College of Engineering, Pune University, Pune (Maharashtra), India.
Manuscript received on 21 January 2013 | Revised Manuscript received on 28 January 2013 | Manuscript published on 30 January 2013 | PP: 153-156 | Volume-1 Issue-6, January 2013 | Retrieval Number: F0438021613/2013©BEIESP
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Abstract: One of the most important task of Wireless Sensor Network (WSN) is data collection . In sensor network the sensors are sensing the information and will be collected by the sink node with multi hoping. In such a scenario the energy is consumed by the node is more. In recent years the researchers are focusing on how to minimize the energy of the node and how it will help to improve the life of the node. One of the idea to do this is minimize the hop. The proposed framework is maximizing the lifetime of the wireless sensor networks (WSNs) by using a mobile sink. Proposed work is having the cluster with cluster head. The mobile sink moves towards the cluster head only upon the occurrence of an event .The cluster head is collecting the data from the sensor node and storing the same. Once the data is available to the cluster head, head will inform to the Mobile Sink. The Mobile Sink will move to respective position of the cluster head and data will be collected by Mobile sink.
Keywords: Wireless Sensor Networks, Cluster, Cluster head, Mobile Sink.
Scope of the Article: WSN

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F0439021613

IJRTE Journal — Mon, 14 Nov 2022 06:50:48 +0000

Area Efficient Interpolator Using Half-Band Symmetric Structure
Rajesh Mehra¹, Shaily Verma²
¹Rajesh Mehra, Associate Professor, Department of Electronics & Communication Engineering, National Institute of Technical Teachers Training & Research, Chandigarh, India.
²Shaily Verma, Department of Electronics & Communication Engineering, National Institute of Technical Teachers Training & Research, Chandigarh, India.
Manuscript received on 21 January 2013 | Revised Manuscript received on 28 January 2013 | Manuscript published on 30 January 2013 | PP: 148-152 | Volume-1 Issue-6, January 2013 | Retrieval Number: F0439021613/2013©BEIESP
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Abstract: In this paper a cost effective Interpolator has been designed and simulated. An area efficient method has been presented to implement cost effective interpolator for wireless communication systems. Interpolator is particularly useful for smoothing signals such as sinusoids or baseband I/Q waveforms. For these signals, interpolation filter is used to accurately produce new samples of the waveform without reducing signal quality. In this paper three structures for interpolator has been used namely Direct Form FIR Polyphase, Nyquist Filter and Half-Band Low pass Filter. The developed interpolator has been compared for performance and implementation cost using Mat Lab. The results show that the performance of all the designs is almost similar, but cost variation is very high. The Half-Band structure shows 52% of reduction in multipliers as compared to Direct Form FIR Polyphase structure. The Half-Band structure is further implemented in Transposed Structure and Symmetric Structure. The Half-Band symmetric structure shows 27% reduction in multipliers as compared to Direct Form FIR Polyphase, Nyquist Filter and Half-Band Low pass Filter structure to provide cost effective solution for wireless applications.
Keywords: DSP, Filter, FIR, Interpolator
Scope of the Article: Behaviour of Structures

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F0448021613

IJRTE Journal — Mon, 14 Nov 2022 06:46:00 +0000

Isolation, Spectral Characterization, Thermal Efficiency and Microbial Evaluation Studies on Indian Rubber (Hevea Brasiliensis) Seed Oil
Sundaram Arvind Narayan¹, Sutha Shobana², Anand Sundaram³, Jeyaprakash Dharmaraja⁴
¹Sundaram Arvind Narayan, Prof., Department of Electrical and Electronic Engineering and Energy, K.N.S.K. College of Engineering, Therakalputhoor, Kanyakumari (Tamil Nadu), India.
²Sutha Shobana, Prof., Department of Chemistry, K.N.S.K. College of Engineering, Therekalputhoor, Kanyakumari (Tamil Nadu), India.
³Anand Sundaram, Prof., Department of Chemistry and Biochemistry, University of Maryland, Baltimore County, Maryland USA.
⁴Jeyaprakash Dharmaraja, Prof., Department of Division of Chemistry, Faculty of Science and Humanities, Sree Sowdambika College of Engineering, Aruppukottai, Virudhunagar (Tamil Nadu), India.
Manuscript received on 21 January 2013 | Revised Manuscript received on 28 January 2013 | Manuscript published on 30 January 2013 | PP: 143-147 | Volume-1 Issue-6, January 2013 | Retrieval Number: F0448021613/2013©BEIESP
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Abstract: Hevea brasiliensis rubber seeds were collected and were extracted by using n-hexane as the solvent in the Soxhlet Extractor. The extracted semi drying oil was characterized by various physio-chemical and thermal properties. Fatty acid composition of the lipid was investigated using gas chromatography techniques. Vibrational studies of the oil show that the characteristic strong absorption at 1741 and 1644cm-1 for –C=O and –C=C– groups respectively. Both the 1H NMR and 13C NMR spectral studies indicate that the presences of triacylglycerol groups were saturated as well as unsaturated in nature. Photo pyroelectric technique (PPE) was used for thermal characterization of the extracted oil. The effect of the fuels on engine components and exhaust gas emissions such as total hydrocarbon, carbon monoxide, and smoke and brake specific fuel consumption were also investigated. Antimicrobial activity was compared with the standard control drug of chloramphenicol at a concentration of 10 μg/ml at 30, 37 and 42 oC
Keywords: Hevea Brasiliensis Rubber Seeds, Photo Pyroelectric Technique, Spectral Studies, Thermal Emissions, Microbial Screening.
Scope of the Article: Thermal Engineering

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F0445021613

IJRTE Journal — Mon, 14 Nov 2022 06:37:50 +0000

Design and Analysis of High Performance Double Edge Triggered D-Flip Flop
Ravi.T¹, Irudaya Praveen.D², Kannan.V³
¹Ravi.T, Research Scholar, Sathyabama University, Chennai (Tamil Nadu), India.
²Irudaya Praveen.D, M. Tech. Student, Department of VLSI Design, Sathyabama University, Chennai (Tamil Nadu), India.
³Kannan.V, Principal, Jeppiaar Institute of Technology, Kunnam (Tamil Nadu), India.
Manuscript received on 21 January 2013 | Revised Manuscript received on 28 January 2013 | Manuscript published on 30 January 2013 | PP: 139-142 | Volume-1 Issue-6, January 2013 | Retrieval Number: F0445021613/2013©BEIESP
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Abstract: The power consumption of a system is a crucial parameter in modern VLSI circuits especially for low power applications. This paper proposed a new Double Edge Triggered D-Flip Flop (DETFF) which is suitable for low power applications. The proposed DETFF is having less number of clocked transistors than existing designs. The proposed DETFF is simulated with different clock frequencies ranging from 1MHz to 2GHz. Simulation results show lowest average power and least delay than existing designs. Further, the average power and the PDP are improved by 77.23% and 89.11% when compared with existing design respectively, which claims that proposed design is suitable for low power and high performance applications.
Keywords: DETFF, Power, Delay, PDP
Scope of the Article: High Performance Computing

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F0444021613

IJRTE Journal — Mon, 14 Nov 2022 06:32:52 +0000

Thermodynamic Modelling for Performance Analysis of Compression Ignition Engine Fuelled With Biodiesel and its Blends With Diesel
Sanjay Patil
Prof. Sanjay Patil, Department of Automobile Engineering, Guru Nanak Dev Engineering College, Bidar (Karnataka), India.
Manuscript received on 21 January 2013 | Revised Manuscript received on 28 January 2013 | Manuscript published on 30 January 2013 | PP: 134-138 | Volume-1 Issue-6, January 2013 | Retrieval Number: F0444021613/2013©BEIESP
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Abstract: In this work, computer simulation framework for compression ignition engine cycle simulation is developed and engine performance is predicted. Double wiebe’s function is used to model the rate of heat release due to combustion to predict heat released during premixed as well as diffusive phase of combustion. Effect of convective heat transfer and variation in specific heat of test fuels are also considered during development of model. Suitable correlations are established between adjustable parameters of wiebe’s function, relative air-fuel ratio and engine operating conditions, such that the simulated heat release profile matches closely with experimental results. The simulation model is used to analyze the performance, combustion and emission characteristics of single cylinder 3.5 kW rated power diesel engine fuelled with Diesel (D0), Palm Oil Methyl Ester (POME) and POME-diesel blends. The model validation is done by comparing the predicted parameters like brake thermal efficiency and in-cylinder pressure with experimental results and are found in closer approximation. The model is also used to predict net heat release rate, exhaust gas temperature, NOx and soot.
Keywords: Biodiesel, C. I. Engine, POME, Simulation
Scope of the Article: Machine Design

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F0437021613

IJRTE Journal — Mon, 14 Nov 2022 06:28:21 +0000

FPGA Based Cost Efficient Fir Filter Using Factored CSD Technique
Kanu Priya¹, Rajesh Mehra²
¹Er. Kanu Priya, Department of Electronics & Communication, Punjab Technical University, GGSCMT, Kharar (Panjab), India.
²Er. Rajesh Mehra, Department of Electronics & Communication, Punjab Technical University, NITTTR, Chandigarh, India.
Manuscript received on 21 January 2013 | Revised Manuscript received on 28 January 2013 | Manuscript published on 30 January 2013 | PP: 130-133 | Volume-1 Issue-6, January 2013 | Retrieval Number: F0437021613/2013©BEIESP
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Abstract: In this paper, an FPGA based area and power efficient FIR filter for wireless communication systems is presented. The implementation is based on Factored Canonic signed digit (FCSD) which eliminates the use of embedded multipliers. The proposed FIR filter has been implemented using Equiripple Symmetric structure on an FPGA. The developed FIR filter has been optimized in terms of MAC operation using symmetric structure. The symmetric structure requires less hardware for implementation as compared to transposed structure and also reduces hardware complexity. The performance of both symmetric and transposed structure is almost same but implementation cost varies significantly. A 20 tap FIR filter has been designed and simulated using 16 bit input and output precision with the help of Matlab. Factored Canonic signed digit (FCSD) approach is used to implement an FIR Filter taking optimal advantage of the look up table structure of FPGA. The behavioural simulation of proposed VHDL model has been performed using Modelsim simulator. The simulated model has been synthesized using Xilinx synthesis tool (XST) on Virtex 2 based xc2v3000-4ff1152 target FPGA device. The results show that symmetric FIR filter require 52.3 % less hardware as compare to transposed FIR structure. The developed symmetric FIR structure can operated at a maximum frequency of 45 MHz by consuming 6% slices, 2% flip flops and 5% Look up tables (LUTs) to provide cost effective solution for Digital Signal Processing Applications.
Keywords: DSP, FCSD, FIR, FPGA, VHDL
Scope of the Article: FPGAs

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F0436021613

IJRTE Journal — Mon, 14 Nov 2022 06:24:32 +0000

A Survey on Polarization Reconfigurable Patch Antennas
Uma Shankar Modani¹, Anubhav Kanwaria²
¹Dr. Uma Shankar Modani, Department of Electronics & Communication, Government Engineering College, Ajmer (Rajasthan), India.
²Mr. Anubhav Kanwaria, Department of Electronics & Communication, Government Engineering College, Ajmer (Rajasthan), India.
Manuscript received on 21 January 2013 | Revised Manuscript received on 28 January 2013 | Manuscript published on 30 January 2013 | PP: 126-129 | Volume-1 Issue-6, January 2013 | Retrieval Number: F0436021613/2013©BEIESP
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Abstract: Polarization reconfigurability in a microstrip patch antenna system is one of the desired characteristics that have been the focus of research in recent years. Reconfigurable antenna with ability to radiate in more than one polarization state offers several degrees of freedom to antenna designer. The researches on polarization reconfigurable antennas are categorized into simple and complex feed structures. In this paper, several polarization reconfigurable antenna designs with and without loading which have been reported in the literature are discussed.
Keywords: Loading, Microstrip Patch Antenna, Polarization, Reconfigurable Antenna.
Scope of the Article: Smart Antenna

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